1. Field of the Invention
The present invention relates to a method for fabricating a shallow trench isolation (STI) structure. More particularly, the present invention relates to a method for fabricating a shallow trench isolation structure filled with doped silicon dioxide.
2. Description of the Related Art
In an integrated circuit, an isolation structure is needed to isolate devices. Since a shallow trench isolation structure has advantages of scalability and a good isolation ability, this technology is preferably used in the sub-micron process.
In the conventional method for forming a shallow trench isolation structure, an anisotropic etching process is performed with silicon nitride serving as a mask to form a steep trench in a substrate. An undoped silicon dioxide layer is formed within the trench and a shallow trench isolation structure is thus formed. The substrate is then dipped in a dilute hydrofluoric acid (HF) solution to remove impurities formed during the above processes.
Usually, a portion of the undoped silicon dioxide layer is lost during the subsequent dipping process so that defects are formed in the undoped silicon dioxide layer mid the reliability of the shallow trench isolation structure is decreased. An annealing, process is performed at about 1100.degree. C. to densify the undoped silicon dioxide layer before the dipping process to prevent the undoped silicon dioxide layer from losing material.
However, due to a large difference in thermal expansion coefficients and Young's modulus between the substrate and the undoped silicon dioxide layer, significant substrate stress of several hundred MPa occurs during the annealing process. Due to this stress, crystallographic detects occur in the undoped silicon dioxide layer, which defects enhance junction leakage and sub-threshold leakage. In dense pattern areas and high packing density memory devices, this causes the devices to fail.